1. Field of the Invention
The present invention relates to a frequency control system for extracting a clock signal from a high bit rate digital signal or for synthesizing a frequency. The system comprises a circuit loop including a voltage-controlled oscillator (VCO) slaved to an incoming signal of unstable frequency.
2. Description of the Prior Art
The frequency control of a VCO is used in a receiver in order to extract from a digital data signal an original clock signal produced by a transmitter which transmitted the data signal. Frequency synthesis using a VCO is used in radio transmitters and receivers when it is necessary to generate precise frequencies for selecting a channel. In these two applications, the main technical problem is to extract the clock signal contained in the received digital data signal, which is affected by noise, i.e. which contains jitter, and to synthesize a precise frequency based on an unstable reference frequency.
The invention has applications in the field of digital transmissions at high bit rates, up to several hundred Mbit/s, for recovering the clock signal needed to process the received data, and in the field of radio equipments, for synthesizing high frequencies, typically up to a few GHz.
In the two fields of applications previously cited, it is standard practice to use a phase-locked loop (PLL) which comprises a VCO, a frequency divider which can be programmable and which is connected to the output of the oscillator to provide a divided frequency signal, and a phase comparator which delivers an error signal based on comparing the phases of the divided frequency signal and a reference signal. The amplified and then filtered error signal controls the oscillator VCO.
A first difficulty encountered in the prior art, when the required frequency is high, is that of providing a divide-by-N frequency divider which is needed to synthesize any frequency equal to k.N.Fr where k is a constant, N is a variable coefficient and Fr is the frequency of the reference signal. If N is an integer, frequencies multiple of the frequency Fr of the reference signal are generated by the oscillator VCO. However, it is routine practice not to limit N to integer values, which increases the complexity of the frequency divider included in the loop and leads to insurmountable technical implementation constraints at high frequencies.
A second difficulty results from the necessity to apply a very stable reference signal to the phase comparator; if this is not achieved, noise in the reference signal is multiplied by a factor k.N in the synthesized signal output by the oscillator.
The main object of this invention is to overcome the aforementioned difficulties by providing a frequency control system which is based on comparing the frequencies of an incoming digital signal which has an unstable clock frequency and a clock signal generated directly or indirectly by an oscillator VCO and which is used both to extract the clock signal and for frequency synthesis, with the aim of tolerating variation in the frequency of the incoming signal about a mean value without any effect on the clock signal to be extracted or on the clock signal to be synthesized, whose frequency remains stable even in the presence of high jitter in the incoming signal.
Accordingly, a frequency control system comprising voltage-controlled oscillator means generating a clock signal, means receiving a digital incoming signal with unstable frequency for sampling the clock signal at two pairs of times corresponding to two consecutive transitions of the incoming signal in response to each of predetermined transitions of the incoming signal, the times of one pair being separated by a predetermined time-delay at most equal to half the period of the clock signal, to produce four state signals of the clock signal, a frequency comparator combining the four state signals to form an upcounting signal only when the frequency of the clock signal is substantially less than the frequency of the incoming signal and to form a downcounting signal only when the frequency of the clock signal is greater than the frequency of the incoming signal, and upcounting and downcounting means for respectively upcounting and downcounting predetermined transitions of the incoming signal in response to the upcounting signal and the downcounting signal in order to apply a control voltage depending on a content of the upcounting and downcounting means to the oscillatory means.
The frequency comparison in accordance with the invention is effected on the basis of two transitions of the incoming signal and not on one transition, as is generally the case in the prior art. The four state signals resulting from sampling the incoming signals at the two pairs of times for each transition can be combined by means for producing the upcounting signal for as long as three of the state signals corresponding to consecutive sampling times of the clock signal are identical, and means for producing the downcounting signal for as long as one of two state signals corresponding to sampling times of the clock signal lying between sampling times of the clock signal corresponding to the other two state signals is different from the other three state signals.
In a preferred embodiment of the invention, the functions of the aforementioned two producing means are implemented in the frequency comparator by means of a first EXCLUSIVE-OR gate receiving two state signals corresponding to sampling times of the clock signal between which are sampling times of the clock signal corresponding to the other two state signals, a second EXCLUSIVE-OR gate receiving the other two state signals, a first AND gate connected directly to the first EXCLUSIVE-OR gate and via an inverter to the second EXCLUSIVE-OR gate to produce said upcounting signal and a second AND gate connected directly to the second EXCLUSIVE-OR gate and via an inverter to the first EXCLUSIVE-OR gate to produce the downcounting signal.
The sampling means comprises preferably means for detecting predetermined transitions in the incoming signal in order to produce a transition signal and another transition signal delayed by the predetermined time-delay, and two pairs of flip-flops respectively producing the state signals. Each pair of flip-flops has a first flip-flop receiving the clock signal and a second flip-flop having an input connected to the direct output of the first flip-flop. The transition signal and the delayed transition signal are respectively applied to clock inputs of the pairs of flip-flops.
In particular, when the incoming signal is a clock signal with an unstable frequency, the sampling means is entirely digital. In this case, the transition detecting means comprises a divide-by-four frequency divider to produce a clock signal at half the frequency of the incoming signal, and means for selecting a transition of said incoming signal and a transition in the complementary signal of the incoming signal when it has been complemented, during one half-period in two of the half-frequency clock signal in order to produce the transition signal and the delayed transition signal, respectively.
When the frequency control system is used to extract a clock signal contained in an incoming digital data signal affected by noise, the system comprises means connected to the sampling means for comparing the phases of the incoming signal and the clock signal as a function of two of the four state signals in order to select from the clock signal and the complementary signal thereof an outgoing clock signal which is more in phase with the incoming signal and which is used to read the incoming signal. In this way, the outgoing clock signal is the recovered clock signal originally produced by the transmitter.
In a preferred embodiment of the invention, the phase comparing means comprises latch logic means connected to the sampling means for selecting from the clock signal and the complementary signal thereof an outgoing clock signal which is more in phase with the incoming signal when the state signals produced by the first or second flip-flops of said pairs of flip-flops are respectively at first and second states and at second and first states, and a flip-flop for reading the incoming signal as a function of the outgoing clock signal.
When the frequency control system is used to synthesize frequencies, it comprises divider means for generating the input signal to be applied to the sampling means in the form of an unstable reference clock signal having a mean frequency over a respective number of periods equal to a programmed frequency from a unit clock signal having a stable frequency not less than four times the programmed frequency, the ratio between the programmed frequency and the respective number of periods being constant.
The frequency of the unit clock signal is therefore more than four times the highest frequency that can be programmed in the programmable frequency divider.
The reference clock signal has a variable frequency resulting from programmed integer or non-integer division of the stable frequency of the unit clock signal, which is delivered by a quartz-crystal-controlled clock, for example. Variation of the reference signal frequency is inhibited in the control loop consisting essentially of the sampling means, the frequency comparator, the upcounting and downcounting means and the oscillator, with the result that the synthesized frequency produced by the oscillator is the required stable frequency, which is equal to a multiple of the mean reference clock frequency. In contrast to the prior art, the invention replaces the programmable frequency divider of prior art synthesis loops with a fixed frequency divider.
Frequency divider means comprises in a preferred embodiment of the invention an adder and a buffer register clocked at the frequency of the unit clock signal and storing a sum at outputs of the adder, wherein the adder adding the sum to the respective number associated with the programmed frequency.
To eliminate any distortion of the duty cycle of the reference clock signal, frequency divider means comprises a divide-by-two frequency divider receiving the most significant bit of the sum from the buffer register to generate the reference clock signal.
For the application to frequency synthesis in particular, oscillatory means comprises at least one voltage-controlled oscillator controlled by the upcounting and downcounting means via a loop filter, and a frequency divider for dividing the frequency of the signal generated by the oscillator by a fixed ratio in order to generate the clock signal. The fixed ratio is preferably a power of two. The loop filter filters in particular harmonics of the unit clock signal resulting from frequency division in the programmable frequency divider.